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The increasing number of radio protocols along with the need for multimedia support in mobile communication devices call for heterogeneous, programmable multi-core processors. This paper presents a fully programmable, heterogeneous single chip SDR platform with multimedia support, fabricated in a 0.13 ?m CMOS process. Running at 175 MHz, a peak performance of 40 GOPS is delivered while dissipating 1.5 W. The typical MPSoC programmability problem is solved with a dedicated hardware unit which performs dynamic spatial and temporal mapping of tasks onto processing elements.
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