Download now Free registration required
This paper presents a hardware implementation for the HB++ authentication protocol. The design is efficient enough to be used in resource constrained pervasive devices like RFID tags or sensor motes. The architecture has been developed targeting the RFID environment, it has 8 bit data path along with a control unit and has been implemented on Altera's FPGA and CPLD platforms (Cyclone and MAX II) using the Quartus software. A detailed analysis of the implementation in terms of resource usage is also discussed.
- Format: PDF
- Size: 487.4 KB