A High-Level Mapping Algorithm Targeting 3D NoC Architectures With Multiple Vdd

The communication problem in modern ICs becomes a challenge issue. This paper introduces a high-level mapping algorithm targeting to low-power 3D NoC devices. By appropriately assigning application's functionalities to layers with different supply voltages the authors achieve reasonable energy savings and temperature reduction. Additionally, their methodology supports real-time adaption on different traffic scenarios. Experimental results show that energy savings up to 19% are feasible, without any area and delay overhead, as compared to architectures powered by only one supply voltage.

Provided by: National Technical University of Athens Topic: Mobility Date Added: Apr 2010 Format: PDF

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