A High Speed and Efficient Design for Binary Number Squaring Using Dwandwa Yoga

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The complexity in implementing complex logic functions in hardware circuitry is to be reduced in order to perform large calculations with minimum delay. This paper presents a most efficient and high speed design for doubling a binary number using Dwandwa Yoga logic, a squaring algorithm. The calculation is performed based on the "Duplex" D property. This method reduces the carry propagation delay when compared to the other Vedic multiplication algorithms and conventional multiplication algorithms to a great extent. As the number of bits increases the size of the hardware circuitry decreases to a great extent by using the proposed logic.