Date Added: Jan 2012
In this paper, a compact and fully pipelined ASIC implementation of AES cryptography algorithm has been presented. The proposed implementation is configurable to take 128, 192 and 256-bit keys according to the requirement of the security level. The proposed architecture is synthesized in 180 nm standard cell CMOS technology and simulated at gate level to measure the speed of operation. The proposed implementation with 32-bit I/O gives a maximum of 10.656 Gbps throughput with the maximum operating frequency of 333 MHz which outperforms the previously reported schemes.