Processors

A Locked Cache-Based Synchronization Protocol for CMP

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Executive Summary

CMP processors are already replacing complex single core superscalar processor architectures. They offer better performance per watt and area. This is especially true in TLP rich server and web applications. Process / thread synchronization is important since CMP consists of multiple processor cores sharing cache resources including shared data structures. This work proposes a locked cache-based shared memory technique suitable for CMP synchronization. A proposed cache coherence protocol, called Lock-based Cache Coherence Protocol (LCCP) was designed and its performance was compared with well known synchronization primitives (LL, SC) using MESI cache coherence protocol. Experiments were performed on the modified MP-Simplesim simulator to implement current proposal. Simulation results show that LCCP outperforms the MESI protocol on the benchmark programs.

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