A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO
The authors propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-5 and Virtex-6 FPGAs. The architecture is built around a 8-bit datapath. The Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and ECHO at all levels of security. Thanks to a careful organization of AES and ECHO internal states in the register file, they manage to generate all read and write addresses by means of a modulo-16 counter and a modulo-256 counter.