Hardware

A Methodology for Constraint-Driven Synthesis of On-Chip Communications

Free registration required

Executive Summary

The authors present a methodology and an optimization framework for the synthesis of on-chip communication through the assembly of components such as interfaces, routers, buses and links, from a target library. Models for functionality, cost, and performance of each element are captured in the library together with their composition rules. They develop a mathematical framework to model communication at different levels of abstraction from the point-to-point input specification to the library elements and the final implementation.

  • Format: PDF
  • Size: 3317.76 KB