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As technology scales for increased circuit density and performance, the management of power consumption in System-on-Chip (SoC) is becoming critical. Today, having the appropriate Electronic System Level (ESL) tools for power estimation in the design flow is mandatory. The main challenge for the design of such dedicated tools is to achieve a better tradeoff between accuracy and speed. This paper presents a consumption estimation approach allowing taking the consumption criterion into account early in the design flow during the system cosimulation. The originality of this approach is that it allows the power estimation for both white-box Intellectual Properties (IPs) using annotated power models and black-box IPs using standalone power estimators.
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