Date Added: May 2010
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and micro architecture levels. In this paper, the authors propose a multi-level optimization approach, combining techniques at the circuit and micro architecture levels, for reducing the impact of NBTI on the Functional Units (FUs) of a high performance processor core. The authors perform SPICE simulations to evaluate the impact of circuit-level design optimizations to reduce the NBTI guardband in terms of area, delay, and power.