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A New Multiplication Algorithm Using High-Speed Counters

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Executive Summary

In this paper, a new high-speed multiplication algorithm has been presented. A multiplier has three important steps, which include partial product generation, partial product reduction, and final addition. In partial product generation, a new booth algorithm has been presented. In partial product reduction, a new tree structure has been designed and in final addition step, a new hybrid adder using 4-bit blocks has been proposed. A new partial product reduction algorithm using counter architecture is designed. A novel full-adder has been proposed. Simulations have been done with spice and C codes. The proposed multiplier has 13 percent reduction in transistor count, 11 percent improvement in power consumption and 10 percent delay modification in compare with other multiplication algorithms.

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