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Cryptographic pairing (bilinear mapping) is a core algorithm for various cryptography protocols. It is computationally expensive and inefficiently computed with general purpose processors. Although there has been previous work looking into efficient hardware designs for pairing, most of these systems use small characteristic curves which are incompatible with practical software designs. In this paper, the authors propose novel processor architecture for pairing-based cryptography applications using large characteristic curves. It takes advantage of some unique FPGA features such as huge aggregated memory bandwidth and massively parallel computation logic to achieve high performance and high energy efficiency.
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