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A Novel Virtual Grounding Based Read-Error Reduction Technique in SRAM

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Executive Summary

In this paper, the authors are going to modify the Schmitt Trigger based SRAM for the purpose of more reduced power & area than the existing type of designs as well as the new design which is combined of virtual grounding with read error reduction logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area & power factors than the Schmitt Trigger based SRAM designs the simulations were done using microwind & DSCH results.

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