A Quantitative Evaluation of a Network on Chip Design Flow for Multi-Core Consumer Multimedia Applications
A growing number of applications are integrated on the same System on Chip in the form of hardware and software Intellectual Property (IP). Many applications have firm or soft real-time requirements and require bounds on latency and throughput. To accommodate the growing number of application requirements, the on-chip interconnect must offer scalability on the physical, architectural and functional level. Networks on Chip (NoC) are proposed as a scalable communication architecture that is also able to deliver guaranteed performance. Traditionally, NoCs focus on delivering physical and architectural scalability. The functional scalability, i.e., the ability to satisfy an increasing number of increasingly demanding requirements with a constant cost/performance ratio, is often overlooked.