A Reconfigurable High Performance SAMBA Bus for System on Chip Design
Shared bus is the most commonly used bus architecture in System-on-Chip. In order to improve the characteristics of Shared bus, high performance SAMBA bus architecture was proposed. In SAMBA bus, with a single arbitration, multiple bus accesses are allowed to take place simultaneously. Therefore, scalability and bandwidth are higher in SAMBA bus when compared to Shared bus. One drawback of SAMBA bus is, multiple bus accesses are possible only if they are compatible with each other (i.e. the data transfers do not require common bus segments). But if the bus accesses require common bus segments during the data transfer, then multiple bus accesses cannot take place simultaneously. In this paper, a new type of dynamically reconfigurable SAMBA bus is proposed which can overcome the existing drawback.