Processors

A Scalable Micro Wireless Interconnect Structure for CMPs

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Executive Summary

This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to interconnect hundreds to thousands of cores in Chip MultiProcessors (CMPs), where current interconnect technologies face severe scaling limitations in excessive latency, long wiring, and complex layout. This paper proposes a recursive wireless interconnect structure called the WCube that features a single transmit antenna and multiple receive antennas at each micro wireless router and offers scalable performance in terms of latency and connectivity.

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