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Multi-dimensional packet classification is a key function for networking applications in high-speed routers. Although a multitude of research has explored this area, efficient packet classification that supports large rule sets at line rate remains challenging. This paper presents a scalable pipeline architecture, named BiConOLP, for line rate packet classification on FPGAs. The authors study the problem of balancing memory distribution across pipeline stages while keeping overall resource usage low using a multitude of pre and post mapping waste elimination techniques, algorithm optimizations, and customized hardware implementations.
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