A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback

This paper presents an asynchronous FPGA architecture for implementing cryptographic algorithms secured against physical cryptanalysis. The authors discuss the suitability of asynchronous reconfigurable architectures for such applications before proceeding to model the side channel and defining the objectives. The logic block architecture is presented in detail. They discuss several solutions for the interconnect architecture, and how these solutions can be ported to other flavours of interconnect (i.e. single driver)Next They discuss in detail a high speed asynchronous configuration chain architecture used to configure the asynchronous FPGA with simulation results, and they present a 3 x 3 prototype FPGA fabricated in 65 nm CMOS.

Provided by: CNRS Topic: Security Date Added: Mar 2011 Format: PDF

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