A Simple 1-Byte 1-Clock RC4 Design and Its Efficient Implementation in FPGA Coprocessor for Secured Ethernet Communication
In the field of cryptography till date the 1-byte in 1-clock is the best known RC4 hardware design, while the 1-byte in 3clocks is the best known implementation. The design algorithm in considers two consecutive bytes together and processes them in 2 clocks. The design of 1-byte in 3-clocks is too much modular and clock hungry. In this paper considering the RC4 algorithm, as it is, a simpler RC4 hardware design providing higher throughput is proposed in which 1-byte is processed in 1-clock. In the design two sequential tasks are executed as two independent events during rising and falling edges of the same clock and the swapping is directly executed using a MUX-DEMUX combination.