A Simple CMOS PFD for High Speed Applications

Free registration required

Executive Summary

Phase Locked Loop (PLL) is a main block in many applications such as wireless communication systems, digital circuits, and sensors' receivers. It is a clock or carrier generator. These applications need low power blocks to have long life battery. Phase Frequency Detector (PFD) is one of the PLL blocks. The main concept of PFD is comparing two input frequencies in terms of both phase and frequency (Leenaerts et al, 2001). In a PLL the two frequencies are reference frequency (Fref) and the Voltage Controlled Oscillator (VCO) output after division by N (Fvco).

  • Format: PDF
  • Size: 136.75 KB