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As low-power design has become a concern in digital VLSI design, especially for portable and high performance. So leakage current is of prime concern. When the MOSFET is in off-state, a significant leakage current passing through the drain electrode can be detected at drain voltage much lower than the breakdown voltage. Many researchers have attributed the leakage current to the band-to-band tunneling occurring in the overlap region and named the phenomenon Gate-Induced Drain Leakage current (GIDL). This leakage has actually been observed in DRAM trench transistor cells and identified as the dominant leakage mechanism in discharging the storage node. In this paper, the authors have studied different models on GIDL and tried to find out what are the various factors affecting the GIDL.
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