Date Added: Jan 2012
Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper, the authors study the routing constraints of Virtex devices and they propose a systematic methodology for designing a novel general-purpose interconnection network targeting to reconfigurable architectures. This network consists of multiple segment wires and SB patterns, appropriately selected and assigned across the device. The goal of their proposed methodology is to maximize the hardware utilization of fabricated routing resources. The derived interconnection scheme is integrated on a Virtex style FPGA. This device is characterized both for its high-performance, as well as for its low-energy requirements.