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This paper addresses power reduction and performance improvement for wireless Orthogonal Frequency-Division Multiplexing (OFDM) systems using a Dynamic Sample-Timing Controller (DSTC) and Phase-Tunable Clock Generator (PTCG). The receiver, applying the proposed DSTC algorithm, searches for the optimal sampling phase at the symbol rate, instead of the Nyquist rate (or higher), to reduce the extra power consumed in high-rate operations. The proposed PTCG circuits provide the desired clock phase for optimum sampling to improve system performance.
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