Processors

A Task-Centric Memory Model for Scalable Accelerator Architectures

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Executive Summary

This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit 1000-core processors. In these workloads, the authors observe data sharing and communication patterns that can be leveraged in the design of memory systems for future 1000-core processors. Based on these insights, they propose a memory model that uses a software protocol, working in collaboration with hardware caches, to maintain a coherent, single-address space view of memory without the need for hardware coherence support.

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