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The authors describe a model of Field Programmable Gate Array based systems realised with the Stochastic Activity Networks formalism. The model can be used to debug the circuit design synthesised from the high level description of the system, and to calculate the signal probabilities and transition densities of the circuit design, which are parameters that can be used for reliability analysis, power consumption estimation and pseudo random testing. They validate the developed model by reproducing the results presented in other studies for some representative combinatorial circuits, and they explore the applicability of the proposed model in the analysis of real-world devices by analyzing the actual implementation of a circuit for the generation of Cyclic Redundancy Check codes.
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