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The next generation of wireless systems will require low-power multi-standard chipsets that are capable to operate over a number of different communication protocols, signal conditions, battery status, etc. An efficient implementation of these chipsets demands for reconfigurable transceiver blocks that can adapt to the diverse specifications with minimum power consumption and at the lowest cost. One of the key blocks in multi-standard receivers is the ADC, because of the assorted signal bandwidths and dynamic ranges that can be required to properly handle the A/D conversion for several operation modes.
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