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This paper presents a power efficient 64-state Viterbi Decoder (VD) employing a two-stage radix-4 add compare-select architecture. A class of VD architectures is implemented, and their hardware complexity, maximum operating speed, and power consumption are compared. Implementation results show that the proposed VD architecture is suitable for Multi-Band Orthogonal Frequency-Division Multiplexing (MB-OFDM) Ultra-WideBand (UWB) systems, which can support the data rate of 480 Mbps even when implemented using 0.18-?m CMOS technology. Ultra-WideBand (UWB) systems have been receiving much attention in recent years, mainly due to their high data rate capability with low transmit power.
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