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In this paper, the authors present a deep subthreshold 6-T SRAM, which was fabricated in an industrial 0.13 m CMOS technology. The authors first use detailed simulations to explore the challenges of ultra-low-voltage memory design with a specific emphasis on the implications of variability. The authors then propose a single-ended 6-T SRAM design with a gated-feedback write-assist that remains robust deep in the subthreshold regime.
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