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The use of reconfigurable computing for accelerating floating-point intensive codes is becoming common due to the availability of DSPs in new-generation FPGAs. The authors present the design of an efficient, pipelined floating-point datapath for calculating the logarithm function on reconfigurable devices. They integrate the datapath into a stand-alone LUT-based (Lookup Table) component, the LAU (Logarithm Approximation Unit). They extended the LAU, by integrating two architecturally independent, LAU-based datapaths into a larger component, the VLAU (Vector-like LAU).
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