Accumulator Based 3 Weighted Pattern Generation Using of VHDL

In a BIST design, the generation and application of the test vectors and the analysis of the resulting response are part of the circuit (or system) under test. Weighted pseudo-random Built-In Self-Test (BIST) schemes have been used to reduce the number of test vectors for achieving complete fault coverage in BIST applications. 3-weight pattern generation uses only three weights 0, 0.5 and 1. An accumulator-based 3-weight test pattern generation scheme is presented that tests the MAC unit with different multiplier such as Vedic multiplier, Booth multiplier, array multiplier and different adders such as carry look ahead adder, ripple carry adder; the proposed scheme generates set of patterns with weights 0, 0.5, and 1.

Provided by: International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE) Topic: Hardware Date Added: Sep 2014 Format: PDF

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