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On-Chip Interconnection Networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the design of buffers in the router influences the energy consumption, area overhead, and overall performance of the network. In this paper, the authors propose low-power low-area OCIN architecture by reducing the number of buffers within the router. To minimize the performance degradation due to the reduced buffer size, they use the already existing repeaters along the inter-router channels to double as buffers along the channel when required.
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