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As part of the trend towards Chip MultiProcessors (CMPs) for the next leap in computing performance, many architectures have explored sharing the last level of cache among different processors for better performance - cost ratio and improved resource allocation. Shared cache management is a crucial CMP design aspect for the performance of the system. This paper first presents a new classification of cache misses - CII: Compulsory, Inter-processor and Intra-processor misses - for CMPs with shared caches to provide a better understanding of the interactions between memory transactions of different processors at the level of shared cache in a CMP.
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