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In this paper, the authors will present a near-ML (Maximum Likelihood) MIMO (Multiple Input Multiple Output) detector explicitely optimized for parallel programmable baseband architectures, such as DSPs (Digital Signal Processors) with VLIW (Very Long Instruction Word), SIMD (Single Instruction Multiple Data) or vector processing features. First, the authors propose the SSFE (Selective Spanning with Fast Enumeration) algorithm as an architecture friendly near-ML MIMO detector. The SSFE has a distributed and greedy algorithmic structure that brings a completely deterministic and regular dataflow. This enables efficient parallelization on programmable architectures.
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