Adding Aggressive Error Correction to a High-Performance Compressing Flash File System

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Executive Summary

While NAND flash memories have rapidly increased in both capacity and performance and are increasingly used as a storage device in many embedded systems, their reliability has decreased both because of increased density and the use of Multi-Level Cells (MLC). Current MLC technology only specifies the minimum requirement for an Error Correcting Code (ECC), but provides no additional protection in hardware. However, existing flash file systems such as YAFFS and JFFS2 rely upon ECC to survive small numbers of bit errors, but cannot survive the larger numbers of bit errors or page failures that are becoming increasingly common as flash file systems scale to multiple gigabytes.

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