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With the number of cores of Chip MultiProcessors (CMPs) rapidly growing as technology scales down, connecting the different components of a CMP in a scalable and efficient way becomes increasingly challenging. In this paper, the authors explore the architectural-level implications of interconnection network design for CMPs with up to 128 fine-grain multithreaded cores. They evaluate and compare different network topologies using accurate simulation of the full chip, including the memory hierarchy and interconnect, and using a diverse set of scientific and engineering workloads. They find that the interconnect has a large impact on performance, as it is responsible for 60% to 75% of the miss latency.
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