Date Added: Sep 2011
This paper explores the benefit of channel coding for high-speed backplane or chip to chip interconnects, referred to as the high-speed links. Although both power constrained and bandwidth-limited, the high-speed links need to support data rates in the Gbps range at low error probabilities. Modeling the high-speed link as a communication system with noise and Inter Symbol Interference (ISI), this paper identifies three operating regimes based on the underlying dominant error mechanisms. The resulting framework is used to identify the conditions under which standard error control codes perform optimally, incur an impractically large overhead, or provide the optimal performance in the form of a single parity check code.