An Efficient Static Ram Cell Design for Low Power Consumption
A low power Static-Random Access Memory (SRAM) has become a critical component in modern VLSI systems. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. Most probably the power is wasted for the RAM during its writing operation than for reading operation. A low leakage power, using 180-nm is used. The stand-by leakage power of a SRAM bit memory cell array incorporating a newly-developed leakage current reduction circuit called a "Self-controllable Voltage Level (SVL)" circuit was only 3.7nW, which is 5.4% that of an equivalent conventional memory-cell array at a VDD of 1.8V.