An Evaluation of New Processor Instructions for Accelerating Selected Cryptographic Algorithms

While there are a plethora of cryptographic techniques, the cost to implement them in terms of wall clock execution time and cost has prevented some adoptions from being practical. Up to date, high performance cryptographic performance may require expensive dedicated hardware which could rely upon proprietary API's to construct applications. The implementation of Intel's AES-NI and CLMUL instructions into the Xeon DP processor family allows cryptographic techniques within the network stall cycle of the computer.

Provided by: VeriSign Topic: Data Centers Date Added: Jun 2010 Format: PDF

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