An Explicit Crosstalk Aware Delay Modelling for On-Chip RLC Interconnect for Ramp Input With Skin Effect
With the increase in frequency towards the Giga hertz range, the analysis of high frequency effects like skin effect etc. are becoming extensively predominant and important for high speed VLSI design. Skin effect attenuates the high frequency components of a signal more than that of the low frequency components. Noise produced in any interconnect segment may degrade the performance of the entire system. Hence accurate noise and delay modeling for RLC lines is critical for timing and system integrity analysis. Skin effect alters the values of the resistance and also the inductance, which in turn affects the system integrity in particular and its response as a whole.