An FPGA Based Overlapped Quasi Cyclic Ldpc Decoder for Wi-Max

In this paper, the authors present a partially parallel Quasi cyclic Low Density Parity Check (LDPC) decoder architecture for WiMAX IEEE 802.16e standard. Two phase message passing min-sum decoding algorithm is used to decode the Low Density Parity Check (LDPC) codes. The decoder is designed for code rate

Provided by: Journal of Theoretical and Applied Information Technology Topic: Big Data Date Added: May 2014 Format: PDF

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