Download now Free registration required
FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, the authors suggest to partition a Network-on-Chip (NoC) based system into smaller sub-systems each with their own NoC, and each of which is implemented on a separate FPGA board. Multiple SoC ASICs can be bridged in the same way. The scheme that interconnects the sub-systems should offer the application connections the required Quality of Service (QoS).
- Format: PDF
- Size: 196.52 KB