An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection

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Executive Summary

The authors present a novel scan architecture for simultaneously reducing test application time and test power (both average and peak power). Unlike previous works where the scan chain is partitioned only based on the excitation properties of the Flip-Flops (FFs), the work considers both the excitation and propagation properties of the scan FFs. In the proposed scan architecture, the scan chain is partitioned to maximize the overlapping between the excitation and propagation on different fault sets.

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