An Overview of Achieving Energy Efficiency in On-Chip Networks
Energy efficient NoC design is necessary to optimise power consumption at SoCs and CMPs. Energy efficiency can be achieved through careful optimisation at different levels, such as component, circuit, and architectural level. This paper reviewed different techniques and tools to achieve energy efficiency at each of the aforementioned levels. Adopting a combination of techniques each aiming at different level is presumably the most viable approach in designing energy efficient interconnection network. That said, one must also tackle thermal issues for the NoC to be truly implementable.