Analysis and Implementation of Modified Feedthrough Logic for High Speed and Low Power Structures
In this paper, the design of a low power and high performance dynamic circuit using a new CMOS domino logic family called feed-through logic is presented. The need for faster circuits with low power dissipation has made it common practice to use feed-through logic. The proposed circuit for low power improves dynamic power consumption as compared to the existing feed-through logic and improves its speed. The proposed circuit is simulated using 90nm with power supply 0.9V CMOS process technology from Cadence (R) Virtuoso (R).