Analysis of Partial-Select Concern Free SRAM with Low Leakage Power
Low-power has been a major concern in all real time application and the memory plays a crucial part in VLSI as it holds the temporary instructions and data needed to complete the tasks. This memory consumes power to a greater extent. For this criterion, a new 8T SRAM design is presented using 0.18um CMOS technology. This SRAM design gives a better performance at VDDmin than the other conventional SRAM cells. Another major problem underwent during write operation in SRAM is partial-selection of cells.