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Previous studies have shown that wireless DSP algorithms exhibit high levels of Data Level Parallelism (DLP). Commercial and research work in the field of Software Defined Radio (SDR) has produced designs utilizing Single-Instruction Multiple-Data (SIMD) execution units to exploit this high level of parallelism. These designs have been able to deliver the efficiency and computational power needed to process 3G wireless technologies. Though efficient 3G processing has been achieved, next generation 4G SDR technology requires 10-1000x more computational performance but limits the power budget increase to 2-5x.
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