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To meet increasing performance requirements of DSP applications, application specific processor designs, e.g. Function Unit (FU) duplication and Register File (RF) distribution, are widely used in the design of DSP processors. In this paper, an application specific approach is proposed for the design of interconnection network in such DSP processors. By extracting the scheduling information of DSP applications, the authors decide the minimal number of required partially connected buses. Without impacting the performance and increasing the hardware cost, it provides optimized future scheduling flexibility.
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