Architectural Optimization of AES Transformations and Keyexpansion
Advanced Encryption Standard (AES), is a cryptographic algorithm used for data protection. Designing an efficient hardware architecture for AES with small hardware resource usage is a challenge. Many works are going on for the efficient implementation of AES. The cost and power consumption of the AES can be reduced considerably by optimizing the architecture of AES. AES uses different data transformations such as AddRoundKey, SubByte, ShiftRow and MixColumn transformation and KeyExpansion block. In that, the two expensive transformations in terms of computational resources are MixColumns and SubBytes transformations. In this paper, new techniques for the ASIC implementation of the above transformations and KeyExpansion block are proposed.