Architectural Support for Reducing Parallel Processing Overhead in an Embedded Multiprocessor

The host-multi-SIMD Chip MultiProcessor (CMP) architecture has been proved to be an efficient architecture for high performance signal processing which explores both task level parallelism by multi-core processing and data level parallelism by SIMD processors. Different from the cache-based memory subsystem in most general purpose processors, this architecture uses on-chip ScratchPad Memory (SPM) as processor local data buffer and allows software to explicitly control the data movements in the memory hierarchy. This SPM-based solution is more efficient for predictable signal processing in embedded systems where data access patterns are known at design time. The predictable performance is especially important for real-time signal processing. According to Amdahl's law, the non-parallelizable part of an

Provided by: Institute of Electrical and Electronics Engineers Topic: Mobility Date Added: Jan 2011 Format: PDF

Find By Topic