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Raptor codes are a class of concatenated codes composed of a fixed-rate precode and a Luby-Transform (LT) code that can be used as rate-less error-correcting codes over communication channels. Raptor codes have the atypical features of dynamic code-rate, highly irregular Tanner graph check-degree distribution, random LT-code structure, and LT-precode concatenation. These features render a hardware-efficient decoder implementation achieving good error-correcting performance a challenging task. In this paper, a code construction method targeted at designing hardware efficient decoders is proposed. The 3-stage method, employing an LDPC precode, yields short-cycle-free LT and LDPC codes, decouples code structuring from random encoding and ensures LT-LDPC compatibility.
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